MODEL V 673

128 CHANNEL MULTIEVENT MULTIHIT TDC

Data Sheet

FEATURES

DESCRIPTION

The Model V673 is a 2-unit wide VME 6U module that houses 128 independent Time to Digital Conversion channels. The unit houses 4 TDC chips, developed for the KLOE experiment, thus called from now on the KLOE TDCs.

The KLOE TDC is a multichannel common start/stop time-to-digital converter, with 32 channels per chip. The integrated circuit is developed as a full custom device in 0.5 µm technology, with 1 ns LSB realized using a graycounter working at the frequency of approx. 1 GHz. The chip has four event buffers that allow deadtimeless operations.

The KLOE TDC has been designed at Labe, INFN, Sezione di Roma. Its Design Specifications include the following:

• 32 channels per chip
• 960 MHz working frequency (LSB = 1.0416 ns)
• maximum recording time 64 µs (at 960 MHz - 16 bit range)
• 8 ns double edge resolution
• programmable number of hits per channel (1-16)
• rising/falling edge recording (pulse width measurement)
• individual channel masking
• common START/STOP
• programmable time window
• 4 event buffers
• on chip event counter
• on chip zero suppression
• sequential readout or upon event number request

The unit accepts the following CONTROL signals (ECL differential, 110 Ohm) in common to all channels:

• COM: a common input (START or STOP according to User's selection);
• RST: the RESET signal allows to clear the event buffers and other registers of the unit.

Two special signals ("BUSY", "FULL") are also available on the CONTROL bus. They are ECL signals that allow to obtain a wired-OR Global BUSY (condition that at least one TDC chip has three buffers full) and FULL (condition that at least one TDC chip has all buffers full) signals.

All the above described CONTROL lines can be terminated on-board via internal DIP-switches (termination must be done only on last board in bus).

Three front panel LEDs show the status of the unit:

• DTACK lights up each time the module generates the VME signal DTACK;
• BUSY lights up when at least one TDC chip has three buffers full;
• FULL lights up when at least one TDC chip has all buffers full.

The module houses a VME RORA INTERRUPTER: the interrupt is generated on the condition that at least one TDC chip buffer has data to read out.

The V673 Model uses the P1 and P2 connectors of VME and the auxiliary connector for the CERN V430 VMEbus crate (Jaux Dataway).

The module works in A24/A32 mode; the recognized Address Modifier codes are:

AM=%3F: A24 supervisory block transfer (BLT)
AM=%3D: A24 supervisory data access
AM=%3B: A24 user block transfer (BLT)
AM=%39: A24 user data access
AM=%0F: A32 supervisory block transfer (BLT)
AM=%0D: A32 supervisory data access
AM=%0B: A32 user block transfer (BLT)
AM=%09: A32 user data access

The module's Base Address is fixed by 4 internal rotary switches housed on two piggy-back boards plugged into the main printed circuit board. The Base Address can be selected in the range:

%00 0000 <--> %FF 0000 A24 mode;
%0000 0000 <--> %FFFF 0000 A32 mode.

The data transfer occurs in D16 / D32 mode. D32BLT is also available. The Bus Error generation can be enabled for the Block Transfer cycle termination.

SPECIFICATIONS

CONNECTORS:

1, "CONTROL", input connector, Header 3M type, 5+5 pins, for the common control signals.

DISPLAYS:

SIGNALS:

Input Channels, COMMON:

FULL, RESET, BUSY:

GENERAL:

POWER REQUIREMENTS:

FOR FURTHER INFORMATION: