xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_VCOMP.vhd,
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_3,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_3,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_3,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
fifo_32kx8_dclk_pfull.v,verilog,xil_defaultlib,../../../ip/fifo_32kx8_dclk_pfull/sim/fifo_32kx8_dclk_pfull.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
