trigger paper, corrections

page 2, left side
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2.2. The FPGA-Trigger
The digital FPGA trigger considered here is based on the idea
to generate digital images of the entire Cherenkov camera with
a depth of 1 bit at a rate of about 400MHz and to process the
images with one type of rather inexpensive FPGAs which can
look for pixel coincidences in time and space.The discrimination
of the PMT signals at the level of few PE imposes a basic
signal threshold, but a finer granularity can be obtained by using
more than one threshold and by the generation of one 1-bit
image per threshold per 2.5-ns time slice.

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2.2. The FPGA-Trigger
The digital FPGA trigger considered here is based on the idea
to generate digital images of overlapping pixel regions with
a depth of e.g. 8 bit at a rate of e.g. 100MHz and to process the
images with one type of rather inexpensive FPGAs which can
look for pixel coincidences in time and space.The discrimination
of the PMT signals at the level of few PE imposes a basic
signal threshold, but a finer granularity can be obtained by 
measuring the time over threshold and converting it to the signals
amplitude (by firmware). The time resolution is 1.05 ns.
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page 3, left side
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If the MPT signal exceeds
the treshold a 2.5 ns-long digital LVDS level-0 signal is created
and fed into the cluster-FPGA on the trigger board.

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If the PMT signal exceeds the threshold, a digital (LVDS) level-0 signal
is created and fed into the cluster-FPGA on the trigger board.
The pulse length corresponds to the signals time over threshold.
The minimum detectable input pulse length is about 1ns (FWHM), the
minimum amplitude is about 1mV (limited by the L0 stages electronic noise).
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...
They
are also fed into a 49-pixel trigger fabric which receives the 42
level-0 signals from the 6 neighbouring clusters. At all level-
0 inputs, 49 programmable delays allow the levelling of time
dierences between the channels. The generated level-1 trigger
signal comprises 4 bits and is typically propagated to the central
FPGA. (Question: How do the six trig in/trig out lines work?)

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They
are also fed into a 37-pixel trigger fabric which receives the 30
level-0 signals from the 6 neighbouring clusters. At all level-
0 inputs, 37 programmable delays allow the levelling of time
differences between the channels. The generated level-1 trigger
signal comprises 2 bits and is typically propagated to the central
FPGA. (Question: How do the six trig in/trig out lines work?
-> will not be used in the future)
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The generation of
the level-0 signals takes about 0.4W per pixel (check!). The
power consumption of the FPGA depends on the complexity
of the trigger algorithm executed on the 49 pixels of a cluster.
It was found to vary between 0.2W (check) and 0.4W(check!)
per pixel, so the trigger consumes about 0.8Wper pixel.

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The generation of
the level-0 signals takes about 0.19 W per pixel. The
power consumption of the FPGA varies between 1.5 to 2 W,
depending on the complexity of the trigger algorithm executed
on the 37 pixels.
Overall, the trigger consumes between 0.4W to 0.5W per pixel.
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page 3, right side

...
little compared to the envisaged overall power consumption of
XW per pixel.

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little compared to the envisaged overall power consumption of
2.5 W per pixel.
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The price per pixel
is about 15 which is less than 10% of the typical PMT cost.

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The price per pixel
is about 15 €, which is less than 10% of the typical PMT cost.
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