1. L0-tests

A hardware test bench, the L0-Testboard, see fig. xx,  has been
used to evaluate the L0 trigger stage. The analog input signal, driven
by a pulse generator, passes an attenuator to get signal amplitudes down to 1mV.

The L0 board has a preamplifier, presently adjusted to a gain of 5.
The trigger thresholds DAC can get controlled by the L0-Testboards FPGA 
via a RS232 (or RS485) interface. The thresholds ranges between 0 to 256 mV.

PMT like signals with a minimum amplitude of 1mV are detectable.
Crosstalk and channel to channel skew could not be observed.

2. L1 tests

An efficient way to test the L1 stage, the digital trigger backplane,
is to use two connected boards, see fig. xx, one acting as pattern generator,
while the second is the trigger board.

The pattern generator, simply a particular firmware version, is based on
a look up table of 38bit x 8k (up o 37k). 37 bit are being used to
emulate the 37 L0 signals, while the 38th bit is an "expected trigger" tag.

The pattern time resolution is 1.05 ns. Fixed individual pixel mismatches
(skew emulation) in multiples of about 40 ps can be programmed as well.


3. L0+L1 tests

The above mentioned L0 test board can be used for more complex
setups as well. It's RS485 interface allows to control several (up to 256) boards
in parallel, each jumpered to an inidvidual address. Still one needs
the appropriate number of analog signals. Ideally would be a setup, concisting
out of 7 L0 testboards, equipped with L0 boards and plugged to L1
boards (digital trigger backplanes). 37 PMT tubes or a programmable analog fanout,
driven by a pulse generator, might serve as signal source.