4.1. Trigger Prototype Boards

4.1.1. L0, The Mezzanine Board

The L0 board is a temporary piggy back solution. Later
the L0 stage will be directly soldered on the FE board.
It is powered by +/-3.3V from the FE board. Linear regulators,
the TPS73025DBVT and the LT1964ES5-BYP, generate the +/-2.5V voltage
supply for the seven analog input stages. They comprise an amplifier
of the type LM6629SDE and a ADCMP604BKSZ-R2 comparator.
The differential (LVDS) outputs of the comparator are connected to the
FE boards FPGA.
The amplifier, adjusted to a gain of five, converts the analog signal
from differential to single ended. Its output is connected to the 
postitive input of the comparator circuit. The negative input is driven
by the 8-bit DAC DAC088S085CIMT. The DAC, controlled by the FE board FPGA 
via SPI bus, provides seven L0 thresholds between 0 to 256 mV.

4.1.2. L1, The Digital Trigger Backplane

The L1 board is a hexagonal shaped 8 layer PCB, 125 mm wide.
Main part is a low cost Xilinx FPGA of the type XC6SLX25-2FGG484C. Other parts,
worth to mention, are a DC-DC power supply, a local clock oscillator, two rotating
hexadezimal switches, a 64 bit ID ROM and a temperature sensor.
The FPGA processes 37 L0 signals, seven directly passed through the FPGA of the clusters
FE board while the remaining six times five are being passed via short flat cables from
the neighboring clusters. After power on, the FPGA gets automatically configured by a 
standard PROM. The PROM image can either be altered, using an onboard JTAG connector
or by software from the FE board side.
The DC-DC power supply circuitry, based on a LT3680EMSE, generates 3V, needed by the
two PROMs. Linear regulators of the MCP18268 series, driven by the 3V, are generating the FPGAs
power supply, the 2.5V and the 1.2V .
A local 25Mhz oscillator is connected to the FPGA. The latter can also be clocked
by an external clock. A RJ45 connector is available for the external clock and PPS
connection, the L1 trigger output signal and the L2 trigger input signal. At the same time
this connector can also be used to for the 24V power connection.
The two connectors (TE 6469025-1) in the centre of the bottom side, establish
the signal, power and Gigabit ethernet connection to FE board.
Two general purpose rotating hexadezimal switches are useful, e.g. as clusters position
input to the FPGAs. Additionally each of the six peripheral 50 pin connectors has a
signal pair for the automtical neighbor detection. This way the same firmware can be used,
independant on the cluster position.


4.1.3. L2 Crate
The L2 crate with its components, the Cluster Service Board (CSB) and the L2 Controller 
Board (L2CB), is still in the development phase. It will host 18 CSBs, 1 L2CB and a backplane.
The size is about 50x20x20 cm3. The weight is roughly 11 kg. All boards are powered by the
24V used for powering the 7-pixel clusters. The estimated power consumption is 50 W.


4.1.4. L2, The Cluster Service Board

The Cluster Service Board (CSB) is still in the design phase. It is based on a low cost
Xilinx FPGA as well. On the panel side are sixteen RJ45 connectors, one per cluster,
used for distributing a global clock, PPS and the camera trigger signal. The L1 trigger signal
gets collected via this channel as well. Optional the 24V power for the cluster can be distributed
using the same cable. The board, about 18x16cm in size, has at his back side a
direct connector to be plugged into the backplane of the L2 crate.


4.1.5. L2CB, The Level 2 Controller Board

The L2CB has two interfaces, one pointing outwards from the camera, the other pointing to the inside, establishing the connection to the CSBs. The outside interface has inputs to a central timing unit and an Ethernet port. The Ethernet connection is being used to gather slow control information (e.g. cluster power consumption), for cluster-power switching and for configuring the trigger. Event-number driven time stamps could get transferred via this channel as well. The interface to a timing unit is the connection to
a central clock / PPS source. The inside connection, the L2-crate backplane, carries the clock / PPS signals and the camera trigger. Additionally, there is a bidirectional serial communication channel to
each CSB for exchanging slow control and trigger-configuration-related data.