2.5 FPGA Firmware

The FPGA design can either be asynchronously or synchronously.
Although FPGAs are optimized to run synchronously, driven by one
or several clocks, it is possible to implement a simple trigger,
like the 3NN in a pure combinatorial way.
The first Revsion of the DTB is equipped with an Altera Cyclone IV
FPGA. The Altera development System Quartus allows the very accurate
constraining of the internal delays.
A combinatorial 3NN (of 49 pixel) firmware design showed excellent
results. A L0 signal overlap of 1ns was sufficient to generate a
L1 trigger signal.
For more complex trigger alghorithms, requiring pipelining, the
FPGA has to be used in a synchronous way.
Comparing low cost FPGAs, like ALteras Cyclone IV with Xilinx
Spartan 6, the latter has two advantages.
Firstly, any input pin is equipped with an in system programmable
delay line for delay adjustments of up to 10 ns in step of roughly
40 ps. This allows us to fine tune the individual pixel delays.
Secondly, so called iserdes and oserdes stages are located next
to each pin. The iserdes stage converts a serial bit stream
of up to 950 MSPS into parallel words, up to 8 bit wide.
The word rate is the serial bit rate divide by the word width.
E.g. 800 MSPS at a word width of 8 result in a system clock of
100 MHz. The oserdes stage does the conversion from pararllel to
serial accordingly.
These iserdes stages are being used to sample the L0 signals.
Assuming a sampling rate of 950 MSPS and a serdes factor of 8
gives us 8 time slices of the L0 signal, each 1.05 ns in length.
Eight identical trigger fabrics (eg. 3NN) connected to 37 bits
of a certain time slice, work in parallel.
The resulting 8 bit trigger vector is connected to an 8 bit
oserdes stage, resulting in a single serial trigger signal with
a fixed trigger latency. Due to the sampling of the L0 signals
the latency fluctuates at about +/- 1 ns.
By moving the 8 bit words into shift registers the L0 signals
history can be stored and used for trigger alghorithms based
on time ditribution of individual pixel signals.