4.2. L1, The Digital Trigger Backplane

The Digital Trigger Backplane or L1 board, is a hexagon-shaped 8 layer PCB, 125 mm wide
(see Fig. 5). All elements labeled on the figure are emphasized in the text below with cursive.
Main part is a low cost Xilinx FPGA of the type XC6SLX25-2FGG484C. Other parts,
worth to mention, are a DC-DC power supply, a local clock oscillator, two rotating
hexadezimal switches, a 64 bit ID ROM and a temperature sensor.
The FPGA processes 37 L0 signals. The seven L0s from the central cluster are being
passed through the FE-board FPGA and the FE-board connectors. The remaining thirty
L0 signals are connected to the Xilinx FPGA by using peripheral 50 pin flat cable
connections to the neighbour clusters. The same connections are being used to fanout
the seven L0 signals from the central cluster.
After power on, the FPGA gets automatically configured by a standard PROM. The 
PROM image can be altered, either, by using an onboard JTAG connector or by software
from the FE board side.
The DC-DC power supply circuitry, based on a LT3680EMSE, generates 3V, needed by the
two PROMs. Linear regulators of the MCP18268 series, driven by the 3V, are generating the FPGAs
power supply, the 2.5V and the 1.2V .
A local clock oscillator is connected to the FPGA. The latter can also be clocked
by an external clock. A RJ45 connector is available for Clock_in/PPS_in/L1_out/L2_in.
At the same time this connector can also be used to for the 24V power connection.
The two FE-board connectors (TE 6469025-1) in the centre of the bottom side, establish
the signal, power and FE-board Gigabit ethernet connection.
Two general purpose rotating hexadezimal switches are useful, e.g. as clusters position
input to the FPGAs. Additionally each of the six peripheral 50 pin flat cable connections has a
signal pair for the automatic neighbor detection. This way the same firmware can be used,
independant on the cluster position.
The 64 bit ID ROM assigns a unique ethernet address to the FE-board.
The temperature sensor may be used to compensate for temparature-dependant L0 delay variations.