------------------------------------------------------- -- Design Name : l1a_test_tb -- File Name : l1a_test_tb.vhd -- Function : debugging the "loss of first L1A" feature -- Coder : K.-H. Sulanke, DESY -- Date : 2019-05-08 ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity l1a_test_tb is -- generic( REG_WIDTH : integer := 8; -- BLOCK_SIZE_EXP : integer :=5); end l1a_test_tb; architecture behavior of l1a_test_tb is component dtb4_3nn_015 is generic ( FW_REV : std_logic_vector(15 downto 0) := X"000F"; CLKIN_PERIOD : real := 20.0; -- 50 MHz external clock LCLK_CLKIN_PERIOD : real := 40.0; -- 50 MHz onboard clock PLL_MULT : integer := 20; -- to get 1 GHz from 50 MHz , max. possible serdes rate LCLK_PLL_MULT : integer := 16; -- to get 400 MHz from the 25 MHz oscillator LCLK_DIV : integer := 8; -- to get 50 MHz PLL_DIV : integer := 1; -- affects all pll clock outputs S : integer := 8; -- serdes factor DELCLK_DIV : integer := 8; -- to get 125 MHz iodelay2 clock for a delay range of 0 to 8ns EXTCLK_DIV : integer := 20 -- to get 50 Mhz ); port ( LCLK_ENA : out std_logic; -- LVCMOS, oscillator enable LCLK : in std_logic; -- LVCMOS, local clock input by QOSC GCLKB_P : in std_logic; -- dedicated clock pin, signal from J13-1,2 , LVDS, GCLKB_N : in std_logic; -- external clock + pps input, both are also used as 24V power line J13_BUSY_OUT_P : inout std_logic; -- J13-6,3, DIFF_SSTL2_I, used to transmit the FEB-BUSY signal J13_BUSY_OUT_N : inout std_logic; -- was PPS input before J13_L2_IN_P : inout std_logic; -- J13-4,5, bank2, LVDS, camera trigger input J13_L2_IN_N : inout std_logic; -- from TIB via L2-crate J13_L1_OUT_P : inout std_logic; -- J13-8,7, bank0, LVDS, output, J13_L1_OUT_N : inout std_logic; -- used as pulse shaped L1_out CL0_P : in std_logic_vector (0 to 6); -- bank1, LVDS, from FE-board discriminator CL0_N : in std_logic_vector (0 to 6); -- CL1_P : in std_logic_vector (0 to 4); -- bank3 CL1_N : in std_logic_vector (0 to 4); CL2_P : in std_logic_vector (0 to 4); -- bank3 CL2_N : in std_logic_vector (0 to 4); CL3_P : in std_logic_vector (0 to 4); -- bank3 CL3_N : in std_logic_vector (0 to 4); CL4_P : in std_logic_vector (0 to 4); -- bank1 CL4_N : in std_logic_vector (0 to 4); CL5_P : in std_logic_vector (0 to 4); -- bank1 CL5_N : in std_logic_vector (0 to 4); CL6_P : in std_logic_vector (0 to 4); -- bank1 CL6_N : in std_logic_vector (0 to 4); NBOR_IN : in std_logic_vector (1 to 6); -- low active signals, '0' means neigbor is connected TEST_IO0_P : out std_logic; -- bank0 TEST_IO0_N : in std_logic; -- TEST_IO1_P : in std_logic; -- bank0 TEST_IO1_N : out std_logic; -- TEST_IO2_P : in std_logic; -- bank3 TEST_IO2_N : in std_logic; -- TEST_IO3_P : in std_logic; -- bank3 TEST_IO3_N : in std_logic; -- FANOUT1_P : out std_logic_vector (0 to 4); -- bank0 FANOUT1_N : out std_logic_vector (0 to 4); FANOUT2_P : out std_logic_vector (0 to 4); -- bank2 FANOUT2_N : out std_logic_vector (0 to 4); FANOUT3_P : out std_logic_vector (0 to 4); -- bank2 FANOUT3_N : out std_logic_vector (0 to 4); FANOUT4_P : out std_logic_vector (0 to 4); -- bank2 FANOUT4_N : out std_logic_vector (0 to 4); FANOUT5_P : out std_logic_vector (0 to 4); -- bank0 FANOUT5_N : out std_logic_vector (0 to 4); FANOUT6_P : out std_logic_vector (0 to 4); -- bank0 FANOUT6_N : out std_logic_vector (0 to 4); BUSY_P : in std_logic; -- LVDS BUSY_N : in std_logic; -- FEB-BUSY EXTCLK_P : out std_logic; -- LVDS, connected to FE-board EXTCLK_N : out std_logic; -- TRGL1_P : out std_logic; -- bank2, LVDS, connected to FE-board TRGL1_N : out std_logic; -- TIMEPPS_P : out std_logic; -- bank ?, LVDS, connected to FE-board TIMEPPS_N : out std_logic; -- FPGA_SLOW_0 : in std_logic; -- 2.5V CMOS, SPI_CLK, J12-C6 FPGA_SLOW_1 : in std_logic; -- 2.5V CMOS, SPI_MOSI, J12-D6 FPGA_SLOW_2 : in std_logic; -- 2.5V CMOS, SPI_CE, J12-A7 FPGA_SLOW_3 : out std_logic; -- 2.5V CMOS, SPI_MISO, J12-B7 LT3680_SYNC : out std_logic; -- LVCMOS, 2 Mhz clock (from system clock) nSW1 : in std_logic; -- on board push button, can be used for calibration nLED_ENA : out std_logic; -- '1' disables all LEDs (incl. ethernet jack) nLED_GREEN : out std_logic; -- '0' = LED V3-green is on nLED_RED : out std_logic -- '0' = LED V3-red is on ); --attribute maxskew: string; --attribute maxskew of FANOUT0_P : signal is "1.1 ns"; --attribute maxskew of FANOUT0_N : signal is "1.1 ns"; end component dtb4_3nn_015; signal LCLK_ENA : std_logic := '0'; signal LCLK : std_logic := '0'; signal GCLKB_P : std_logic := '0'; signal GCLKB_N : std_logic := '1'; signal J13_BUSY_OUT_P : std_logic := '0'; signal J13_BUSY_OUT_N : std_logic := '1'; signal J13_L2_IN_P : std_logic; signal J13_L2_IN_N : std_logic; signal J13_L1_OUT_P : std_logic := '0'; signal J13_L1_OUT_N : std_logic := '1'; signal CL0_P : std_logic_vector (0 to 6) := B"000_0000"; signal CL0_N : std_logic_vector (0 to 6) := B"111_1111"; signal CL1_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL1_N : std_logic_vector (0 to 4) := B"1_1111"; signal CL2_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL2_N : std_logic_vector (0 to 4) := B"1_1111"; signal CL3_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL3_N : std_logic_vector (0 to 4) := B"1_1111"; signal CL4_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL4_N : std_logic_vector (0 to 4) := B"1_1111"; signal CL5_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL5_N : std_logic_vector (0 to 4) := B"1_1111"; signal CL6_P : std_logic_vector (0 to 4) := B"0_0000"; signal CL6_N : std_logic_vector (0 to 4) := B"1_1111"; signal NBOR_IN : std_logic_vector (1 to 6) := B"00_0000"; signal TEST_IO0_P : std_logic; signal TEST_IO0_N : std_logic := '1'; signal TEST_IO1_P : std_logic := '0'; signal TEST_IO1_N : std_logic; signal TEST_IO2_P : std_logic := '0'; signal TEST_IO2_N : std_logic := '1'; signal TEST_IO3_P : std_logic := '0'; signal TEST_IO3_N : std_logic := '1'; signal FANOUT1_P : std_logic_vector (0 to 4); signal FANOUT1_N : std_logic_vector (0 to 4); signal FANOUT2_P : std_logic_vector (0 to 4); signal FANOUT2_N : std_logic_vector (0 to 4); signal FANOUT3_P : std_logic_vector (0 to 4); signal FANOUT3_N : std_logic_vector (0 to 4); signal FANOUT4_P : std_logic_vector (0 to 4); signal FANOUT4_N : std_logic_vector (0 to 4); signal FANOUT5_P : std_logic_vector (0 to 4); signal FANOUT5_N : std_logic_vector (0 to 4); signal FANOUT6_P : std_logic_vector (0 to 4); signal FANOUT6_N : std_logic_vector (0 to 4); signal BUSY_P : std_logic := '0'; signal BUSY_N : std_logic := '1'; signal EXTCLK_P : std_logic; signal EXTCLK_N : std_logic; signal TRGL1_P : std_logic; signal TRGL1_N : std_logic; signal TIMEPPS_P : std_logic; signal TIMEPPS_N : std_logic; signal FPGA_SLOW_0 : std_logic := '0'; signal FPGA_SLOW_1 : std_logic := '0'; signal FPGA_SLOW_2 : std_logic := '0'; signal FPGA_SLOW_3 : std_logic; signal LT3680_SYNC : std_logic; signal nSW1 : std_logic := '1'; signal nLED_ENA : std_logic; signal nLED_GREEN : std_logic; signal nLED_RED : std_logic; constant GCLKB_period : time := 20 ns; -- 50 MHz begin GCLKB_GEN: process begin while (true) loop wait for 0 ns; GCLKB_P <= '1'; GCLKB_N <= '0'; wait for GCLKB_period / 2; GCLKB_P <= '0'; GCLKB_N <= '1'; wait for GCLKB_period / 2; end loop; end process GCLKB_GEN; J13_L2_IN_P <= '0', '1' after 1555 ns, '0' after 1595 ns; J13_L2_IN_N <= '1', '0' after 1555 ns, '1' after 1595 ns; -- -- TEST_IO2_GEN: process -- reference clock -- begin -- while (true) loop -- wait for 2 ns; -- TEST_IO2_P <= '1'; -- TEST_IO2_N <= '0'; -- wait for GCLKB_period / 2; -- TEST_IO2_P <= '0'; -- TEST_IO2_N <= '1'; -- wait for GCLKB_period / 2 -2 ns; -- end loop; -- end process TEST_IO2_GEN; -- -- -- TEST_IO3_P <= TEST_IO0_P; -- TEST_IO3_N <= TEST_IO0_N; -- -- pps_del_load <= '0'; -- pps_del_rg <= X"00"; -- -- nSW1 <= '1', '0' after 3111 ns, '1' after 3444 ns; -- REF_SDAT_IN_0_gen: process -- variable i : integer; -- begin -- while (true) loop -- for i in 0 to 255 loop -- wait for 0 ns; -- REF_SDAT_IN_P <= '1'; -- REF_SDAT_IN_N <= '0'; -- wait for 3 ns; -- REF_SDAT_IN_P <= '0'; -- REF_SDAT_IN_N <= '1'; -- wait for 62.34 ns; -- end loop; -- end loop; -- end process REF_SDAT_IN_0_gen; -- instantiate the units under test (uut) UUT_port_map: component dtb4_3nn_015 port map ( LCLK_ENA => LCLK_ENA , LCLK => LCLK , GCLKB_P => GCLKB_P , GCLKB_N => GCLKB_N , J13_BUSY_OUT_P => J13_BUSY_OUT_P, J13_BUSY_OUT_N => J13_BUSY_OUT_N, J13_L2_IN_P => J13_L2_IN_P , J13_L2_IN_N => J13_L2_IN_N , J13_L1_OUT_P => J13_L1_OUT_P , J13_L1_OUT_N => J13_L1_OUT_N , CL0_P => CL0_P , CL0_N => CL0_N , CL1_P => CL1_P , CL1_N => CL1_N , CL2_P => CL2_P , CL2_N => CL2_N , CL3_P => CL3_P , CL3_N => CL3_N , CL4_P => CL4_P , CL4_N => CL4_N , CL5_P => CL5_P , CL5_N => CL5_N , CL6_P => CL6_P , CL6_N => CL6_N , NBOR_IN => NBOR_IN , TEST_IO0_P => TEST_IO0_P , TEST_IO0_N => TEST_IO0_N , TEST_IO1_P => TEST_IO1_P , TEST_IO1_N => TEST_IO1_N , TEST_IO2_P => TEST_IO2_P , TEST_IO2_N => TEST_IO2_N , TEST_IO3_P => TEST_IO3_P , TEST_IO3_N => TEST_IO3_N , FANOUT1_P => FANOUT1_P , FANOUT1_N => FANOUT1_N , FANOUT2_P => FANOUT2_P , FANOUT2_N => FANOUT2_N , FANOUT3_P => FANOUT3_P , FANOUT3_N => FANOUT3_N , FANOUT4_P => FANOUT4_P , FANOUT4_N => FANOUT4_N , FANOUT5_P => FANOUT5_P , FANOUT5_N => FANOUT5_N , FANOUT6_P => FANOUT6_P , FANOUT6_N => FANOUT6_N , BUSY_P => BUSY_P , BUSY_N => BUSY_N , EXTCLK_P => EXTCLK_P , EXTCLK_N => EXTCLK_N , TRGL1_P => TRGL1_P , TRGL1_N => TRGL1_N , TIMEPPS_P => TIMEPPS_P , TIMEPPS_N => TIMEPPS_N , FPGA_SLOW_0 => FPGA_SLOW_0 , FPGA_SLOW_1 => FPGA_SLOW_1 , FPGA_SLOW_2 => FPGA_SLOW_2 , FPGA_SLOW_3 => FPGA_SLOW_3 , LT3680_SYNC => LT3680_SYNC , nSW1 => nSW1 , nLED_ENA => nLED_ENA , nLED_GREEN => nLED_GREEN , nLED_RED => nLED_RED ); end architecture behavior; -- REF_SDAT_IN_0_gen: process -- variable i : integer; -- begin -- while (true) loop -- for i in 0 to 255 loop -- REF_SDAT_IN_P(0) <= '1'; -- REF_SDAT_IN_N(0) <= '0'; -- end loop; -- wait for 3 ns; -- for i in 0 to 255 loop -- REF_SDAT_IN_P(0) <= '0'; -- REF_SDAT_IN_N(0) <= '1'; -- end loop; -- wait for 8 ns; -- end loop; -- end process DISCR_OUT_gen; -- SPI_test: process -- begin -- mr_spi_run <= '0'; -- -- wait until (reset = '0'); -- wait for clk_period * 5; -- -- SPI_WR_RD: for i in 0 to 0 loop -- mr_tx_addr <= B"0000001"; -- reg. write cycle -- mr_tx_data <= X"11"; -- mr_spi_wr <= '1'; -- mr_spi_run <= '1'; -- wait for clk_period *6; -- -- mr_spi_run <= '0'; -- wait until (mr_spi_done = '1'); -- wait for clk_period *60; -- -- -- wait for clk_period * 400; -- wait; -- -- end process SPI_test; -- mr_spi_miso <= sl_spi_miso after 10 ns;