Index of /~sulanke/Projects/CTA/Dig_trigger/NectarCam/L1/rev4/FPGA/dtb4_sources

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory   -  
[TXT]center_pixel_delay_c..>2017-03-06 07:02 2.9K 
[   ]dtb4_3nn_015.ucf 2023-11-23 13:47 23K 
[TXT]dtb4_3nn_015.vhd 2019-05-10 08:59 126K 
[   ]dtb4_3nn_020.ucf 2024-02-29 11:39 23K 
[TXT]dtb4_3nn_020.vhd 2024-02-29 11:42 128K 
[   ]dtb4_3nn_021.ucf 2024-03-04 11:04 23K 
[TXT]dtb4_3nn_021.vhd 2024-03-04 11:04 128K 
[   ]dtb4_3nn_022.ucf 2024-03-20 10:11 23K 
[TXT]dtb4_3nn_022.vhd 2024-03-20 10:07 131K 
[   ]dtb4_3nn_023.ucf 2024-03-22 15:36 23K 
[TXT]dtb4_3nn_023.vhd 2024-06-19 08:01 133K 
[TXT]dtb4_3nn_024.vhd 2024-06-19 08:03 133K 
[TXT]dtb4_3nn_025.vhd 2024-07-12 16:06 133K 
[TXT]dtb4_3nn_026.vhd 2025-02-13 15:57 133K 
[   ]dtb4_3nn_027.ucf 2025-07-07 14:10 23K 
[TXT]dtb4_3nn_027.vhd 2025-07-08 09:25 133K 
[TXT]feb_busy_test_01.vhd 2024-06-26 10:38 4.6K 
[TXT]in_del_1x_03.vhd 2018-03-19 16:06 7.5K 
[TXT]in_del_cl0_02.vhd 2017-12-21 15:05 17K 
[TXT]in_del_cl0_03.vhd 2025-07-07 15:51 18K 
[TXT]in_del_cl1to6_02.vhd 2017-12-21 15:07 17K 
[TXT]in_del_w_cal_01.vhd 2024-03-19 15:36 12K 
[TXT]iserdes_ph_ctrl_02.vhd 2017-10-16 16:53 31K 
[TXT]iserdes_pulse_shaper..>2017-10-16 16:45 9.2K 
[TXT]l1a_test_tb.vhd 2019-05-09 13:39 14K 
[   ]oserdes_01.vhd 2017-10-24 09:00 3.6K 
[TXT]outer_pixel_delay_ca..>2017-03-06 07:04 2.6K 
[TXT]serdes_lh_edge_01.vhd 2017-09-18 14:20 1.8K 
[   ]spi_slave_8bit_02.vhd 2017-09-19 13:31 5.7K 
[   ]sw_led_ctrl_01.vhd 2017-03-31 16:48 5.3K 
[TXT]trig_1_of_37_01.vhd 2017-09-21 16:03 6.1K 
[TXT]trig_pulse_shaper_03..>2017-10-16 15:49 6.9K 
[   ]trigger_3nn_pkg.vhd 2017-12-20 17:27 41K