Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
3,557 |
18,224 |
19% |
|
Number used as Flip Flops |
3,557 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
8,805 |
9,112 |
96% |
|
Number used as logic |
8,738 |
9,112 |
95% |
|
Number using O6 output only |
7,602 |
|
|
|
Number using O5 output only |
193 |
|
|
|
Number using O5 and O6 |
943 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
56 |
2,176 |
2% |
|
Number used as Dual Port RAM |
0 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
56 |
|
|
|
Number using O6 output only |
56 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
0 |
|
|
|
Number used exclusively as route-thrus |
11 |
|
|
|
Number with same-slice register load |
0 |
|
|
|
Number with same-slice carry load |
11 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
2,276 |
2,278 |
99% |
|
Number of MUXCYs used |
268 |
4,556 |
5% |
|
Number of LUT Flip Flop pairs used |
8,857 |
|
|
|
Number with an unused Flip Flop |
5,422 |
8,857 |
61% |
|
Number with an unused LUT |
52 |
8,857 |
1% |
|
Number of fully used LUT-FF pairs |
3,383 |
8,857 |
38% |
|
Number of unique control sets |
680 |
|
|
|
Number of slice register sites lost to control set restrictions |
3,563 |
18,224 |
19% |
|
Number of bonded IOBs |
173 |
232 |
74% |
|
Number of LOCed IOBs |
166 |
173 |
95% |
|
IOB Flip Flops |
1 |
|
|
|
IOB Master Pads |
36 |
|
|
|
IOB Slave Pads |
36 |
|
|
|
Number of RAMB16BWERs |
0 |
32 |
0% |
|
Number of RAMB8BWERs |
1 |
64 |
1% |
|
Number of BUFIO2/BUFIO2_2CLKs |
0 |
32 |
0% |
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
7 |
16 |
43% |
|
Number used as BUFGs |
6 |
|
|
|
Number used as BUFGMUX |
1 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
Number of ILOGIC2/ISERDES2s |
74 |
248 |
29% |
|
Number used as ILOGIC2s |
0 |
|
|
|
Number used as ISERDES2s |
74 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
107 |
248 |
43% |
|
Number used as IODELAY2s |
107 |
|
|
|
Number used as IODRP2s |
0 |
|
|
|
Number used as IODRP2_MCBs |
0 |
|
|
|
Number of OLOGIC2/OSERDES2s |
5 |
248 |
2% |
|
Number used as OLOGIC2s |
1 |
|
|
|
Number used as OSERDES2s |
4 |
|
|
|
Number of BSCANs |
0 |
4 |
0% |
|
Number of BUFHs |
0 |
128 |
0% |
|
Number of BUFPLLs |
5 |
8 |
62% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
0 |
32 |
0% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
2 |
2 |
100% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
4.14 |
|
|
|