dtb4_3nn_025 Project Status
Project File: dtb4_3nn.xise Parser Errors: No Errors
Module Name: dtb4_3nn_025 Implementation State: Translated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
39 Warnings (28 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 3545 18224 19%
Number of Slice LUTs 9323 9112 102%
Number of fully used LUT-FF pairs 2462 10406 23%
Number of bonded IOBs 173 232 74%
Number of Block RAM/FIFO 1 32 3%
Number of BUFG/BUFGCTRLs 7 16 43%
Number of PLL_ADVs 2 2 100%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 12. Jul 16:09:02 2024037 Warnings (28 new)45 Infos (34 new)
Translation ReportCurrentMi 29. Jan 16:36:30 202502 Warnings (0 new)13 Infos (0 new)
Map ReportOut of DateFr 12. Jul 16:10:55 2024   
Place and Route ReportOut of DateFr 12. Jul 16:11:50 2024   
Power Report     
Post-PAR Static Timing ReportOut of DateFr 12. Jul 16:11:59 2024   
Bitgen ReportOut of DateFr 12. Jul 16:14:46 2024   
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateFr 12. Jul 16:15:02 2024
WebTalk Log FileOut of DateFr 12. Jul 16:14:47 2024

Date Generated: 03/24/2025 - 10:26:38