dtb4_3nn_024 Project Status | |||
Project File: | dtb4_3nn.xise | Parser Errors: | No Errors |
Module Name: | dtb4_3nn_024 | Implementation State: | New |
Target Device: | xc6slx16-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 3471 | 18224 | 19% | |
Number of Slice LUTs | 9425 | 9112 | 103% | |
Number of fully used LUT-FF pairs | 2467 | 10429 | 23% | |
Number of bonded IOBs | 173 | 232 | 74% | |
Number of Block RAM/FIFO | 1 | 32 | 3% | |
Number of BUFG/BUFGCTRLs | 7 | 16 | 43% | |
Number of PLL_ADVs | 2 | 2 | 100% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mi 19. Jun 08:04:38 2024 | ||||
Translation Report | Current | Mi 19. Jun 08:51:03 2024 | ||||
Map Report | Out of Date | Mi 19. Jun 08:06:33 2024 | ||||
Place and Route Report | Out of Date | Mi 19. Jun 08:07:29 2024 | ||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Mi 19. Jun 08:07:38 2024 | ||||
Bitgen Report | Out of Date | Mi 19. Jun 08:17:17 2024 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Log File | Current | Fr 12. Jul 16:14:47 2024 |