dtb4_3nn_024 Project Status
Project File: dtb4_3nn.xise Parser Errors: No Errors
Module Name: dtb4_3nn_024 Implementation State: New
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 3471 18224 19%
Number of Slice LUTs 9425 9112 103%
Number of fully used LUT-FF pairs 2467 10429 23%
Number of bonded IOBs 173 232 74%
Number of Block RAM/FIFO 1 32 3%
Number of BUFG/BUFGCTRLs 7 16 43%
Number of PLL_ADVs 2 2 100%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 19. Jun 08:04:38 2024   
Translation ReportCurrentMi 19. Jun 08:51:03 2024   
Map ReportOut of DateMi 19. Jun 08:06:33 2024   
Place and Route ReportOut of DateMi 19. Jun 08:07:29 2024   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of DateMi 19. Jun 08:07:38 2024   
Bitgen ReportOut of DateMi 19. Jun 08:17:17 2024   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentFr 12. Jul 16:14:47 2024

Date Generated: 07/12/2024 - 16:15:03