dtb4_3nn_025 Project Status | |||
Project File: | dtb4_3nn.xise | Parser Errors: | No Errors |
Module Name: | dtb4_3nn_025 | Implementation State: | Translated |
Target Device: | xc6slx16-3csg324 |
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No Errors |
Product Version: | ISE 14.7 |
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39 Warnings (28 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 3545 | 18224 | 19% | |
Number of Slice LUTs | 9323 | 9112 | 102% | |
Number of fully used LUT-FF pairs | 2462 | 10406 | 23% | |
Number of bonded IOBs | 173 | 232 | 74% | |
Number of Block RAM/FIFO | 1 | 32 | 3% | |
Number of BUFG/BUFGCTRLs | 7 | 16 | 43% | |
Number of PLL_ADVs | 2 | 2 | 100% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fr 12. Jul 16:09:02 2024 | 0 | 37 Warnings (28 new) | 45 Infos (34 new) | |
Translation Report | Current | Mi 29. Jan 16:36:30 2025 | 0 | 2 Warnings (0 new) | 13 Infos (0 new) | |
Map Report | Out of Date | Fr 12. Jul 16:10:55 2024 | ||||
Place and Route Report | Out of Date | Fr 12. Jul 16:11:50 2024 | ||||
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Fr 12. Jul 16:11:59 2024 | ||||
Bitgen Report | Out of Date | Fr 12. Jul 16:14:46 2024 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Map Static Timing Report | Out of Date | Fr 12. Jul 16:15:02 2024 | |
WebTalk Log File | Out of Date | Fr 12. Jul 16:14:47 2024 |