Syntax:

• IASH Rd3 BS Rs0 Rs1

Description:

Executes an arithmetic shift right or left of number of bits specified in the content of Rs1 on content of Rs0, and puts the result to Rd3. Right or left shifting is performed depending on positive or negative value, correspondingly, in Rs1. Instruction is executed according to BS (bank select). Instruction is stack conditioned.

Note: When shifting using IASH - sign bit of the source number is preserved.

The algorithm implemented in VHDL for

• IASH Rd3 BS Rs0 Rs1

is the following:

  if(Rs1 >= 0)
    Rd3 = arithmetic shift of Rd0 by (Rd1 % 64) bits to the right
  else
    Rd3 = arithmetic shift of Rd0 by (-Rd1 % 64) bits to the left

Microcode Pattern:

Takes 6 cycles to execute.
    Example: IASH 0xA3 3 0xA0 0xA1

	  
	 MPC  BS3 C3 P3 P1 P0
	---------------------
	 IASH  0  0  00 A1 A0
	  -    0  0  00 00 00
	  -    0  0  00 00 00
	  -    0  0  00 00 00
	  -    0  0  00 00 00
	  -    3  0  A3 00 00

	  

Exceptions :

No exceptions.

Example :

IASH 0x20 3 0x22 0x21 !! Perform arithmetic shift 
                      !! of number of bits = content 
                      !! of 0x21 on content of 0x22 
                      !! then puts the result to 
                      !! register 0x20