The LLL instruction (Load Length and Length) takes the AGU output to load
two different lengths (amount of words) of data for prefetching into cache.
The lengths are loaded into corresponding configuration registers while the
address, that is given to LLL, is encoded as follows:
- Bits [15:0] - length that is loaded into ILENC register.
- Bits [31:16] - length that is loaded into ILEN register.
The length contained in ILEN register is always used by MTI and MTF instructions.
The ILENC register is used by MTFC instruction when the top of the condition stack
is true, otherwise the length in ILEN is taken.
Takes 1 cycles to execute.
Example: LLL
ASELC
-------
LLL
NOT YET
Not available at the moment.