Syntax:

• AGU_RXDR DISP32 Rs1 BS5 Rs2 BS5

Description:

Performs a MULA operation with contents of registers Rs1 and generated address (DISP32), adds content of Rs2 to the MULA result, then loads the final result into AGU accumulator register. The banks of the source registers Rs1 and Rs2 are selected by BS5.

Microcode Pattern:

Takes 5 cycles to execute.
    Example: AGU_RXDR ZERO 5 0x50 0x51

	  
	  DISP     AGU  P5
	------------------
	00000000    -   50
	00000000    -   00
	00000005   RXDR 51
	00000000    -   00
	00000000    -   00

	  

Exceptions :

NOT YET

Example :

AGU_RXDR ZERO 10 0x20 0x21 
  !! Perform MULA with content of
  !! register 0x20 and address 10
  !! Add content of 0x21 to MULA 
  !! result then load the final 
  !! result to AGU accumulator