Syntax:

• AGU_RXD DISP32 Rs5 BS5

Description:

Generates 32-bit address (DISP32), performs a MULA operation with it and the content of register Rs5 (bank selected by BS5). The result is loaded into AGU accumulator register.

Note: DISP32 must be always expressed as a pair "SYMBOL IMMEDIATE". More information on this in notations.

Microcode Pattern:

Takes 4 cycles to execute.
    Example: AGU_RXD ZERO 0xA 0xA5

	  
	  DISP     AGU P5
	-----------------
	00000000    -  A5
	00000000    -  00
	0000000a   RXD 00
	00000000    -  00

	  

Exceptions :

NOT YET

Example :

AGU_RXD ZERO 10 0x20 
  !! Performs MULA with 32-bit 
  !! displacement 10 and the
  !! content of register 0x20
  !! and load the result to 
  !! AGU accumulator register.