Syntax:

• AGU_RSE DISP32 Rs

Description:

Generates 32-bit address (displacement) DISP32, executes logical shift of number of bits specified in displacement on content of register Rs and loads the result into AGU accumulator register. Right or left shifting is performed depending on positive or negative value of DISP32, correspondingly. If the value of displacement exceeds the number of bits in address (64 bits), shift is performed cyclicaly, i.e. on (DISP32 modulus 64) bits.

Note: When performing logical shift - sign bit isn't carried (zero padding)!

Note: DISP32 must be always expressed as a pair "SYMBOL IMMEDIATE". More information on this in notations.

Microcode Pattern:

Takes 3 cycles to execute.
    Example: AGU_RSE ZERO 0x00000041 50

	  
	 DISP    AGU  P5
	-----------------
	00000000  -   A5
	00000000  -   0
	00000041 SHF  0

	  

Exceptions :

NOT YET

Example :

AGU_RSE ZERO 0x00000041 50
   !! Generate 32-bit address (65)
   !! and preforms logical shift
   !! right of number of bits == 1
   !! on contents of register 50. 
   !! Then loads the result to 
   !! AGU accumulator register.