Syntax:

• AGU_RR Rs1 BS5 Rs2 BS5

Description:

Sums the contents of source registers Rs1 and Rs2, then loads the result into AGU accumulator register. The registers Rs1 and Rs2 are accessed via Port 5, their banks are selected by the bank selectors BS5.

Microcode Pattern:

Takes 4 cycles to execute.
    Example: AGU_RR ZERO 0x50 0x51

	  
	AGU P5
	------
	-   50
	-   51
	-   00
	RR  00

	  

Exceptions :

NOT YET

Example :

AGU_RR ZERO 0x20 0x21 
  !! Sums the contents of registers 0x20 
  !! and 0x21 and loads the result to AGU 
  !! accumulator register.