Syntax:

• AGU_ER DISP32 Ra BS5

Description:

Generates 32-bit address (displacement) DISP32, adds it with content of register Ra (64-bit) and then loads it into AGU accumulator register. The register Ra is accessed via Port 5, it's bank is selected via BS5.

Note: DISP32 must be always expressed as a pair SYMBOL IMMEDIATE. More information on this in notations.

Microcode Pattern:

Takes 3 cycles to execute.
    Example: AGU_ER ZERO 0x00000002 0xA5

	  
	  DISP    AGU P5
	----------------
	00000000   -  A5
	00000000   -  00
	00000002   ER 00

	  

Exceptions :

NOT YET

Example :

AGU_ER ZERO 5 0x20 
 !! Generate 32-bit address
 !! (5) add it with contents 
 !! of register 0x20 and load 
 !! it to AGU accumulator.