Syntax:

• AGU_DRR DISP64 Rs1 BS5 Rs2 BS5

Description:

Sums the contents of source registers Rs1 and Rs2 and adds generated 64-bit address (displacement) DISP64 to the sum, then loads it into AGU accumulator register. The registers Rs1 and Rs2 are accessed via Port 5, their banks are selected by the bank selectors BS5 respectively.

Note: DISP64 must be always expressed as a pair "SYMBOL IMMEDIATE". More information on this in notations.

Microcode Pattern:

Takes 4 cycles to execute.
    Example: AGU_DRR ZERO 7 0x50 0x51

	  
	  DISP   AGU P5
	---------------
	00000000  -  50
	00000000  -  51
	00000007 DRR 00
	00000000  -  00 
	
	DISP     AGU P5   B5
	--------------------
	00000000  -  [R0] 0
	[DISPHI]  -  [R1] 1
	[DISPLO] DRR  00  0
	00000000  -   00  0


	  

Exceptions :

NOT YET

Example :

AGU_DRR ZERO 10 0x20 0x21 
  !! Sums the contents of registers 0x20 and 
  !! 0x21. Adds displacement 10 to the resulted 
  !! value and loads the final result to AGU 
  !! accumulator register.