Syntax:

• AGU_DRMR DISP64 Rs1 BS5 Rs2 BS5

Description:

Subtracts content of source register Rs2 from content of source register Rs1, adds generated 64-bit address (displacement) DISP64 to the result and loads it into AGU accumulator register. The registers Rs1 and Rs2 are accessed via Port 5, their banks are selected by the bank selectors BS5.

Note: DISP64 must be always expressed as a pair "SYMBOL IMMEDIATE". More information on this in notations.

Microcode Pattern:

Takes 4 cycles to execute.
    Example: AGU_DRMR ZERO 0x20 0x30 0x31

	  
	 DISP    AGU  P5
	----------------
	00000000  -   30
	00000000  -   31
	00000020 DRMR 00
	00000000  -   00

	  

Exceptions :

NOT YET

Example :

To be added...