Syntax:

• AGU_DR DISP64 Ra BS5

Description:

Loads the content of the source register Ra and adds the generated 64-bit address (displacement) DISP64 , then loads the result into AGU accumulator register. The register Ra is accessed via Port 5, its bank is selected by the bank selectors BS5.

Note: DISP64 must be always expressed as a pair "SYMBOL IMMEDIATE".

Microcode Pattern:

Takes 3 cycles to execute.
    Example: AGU_DR ZERO 10 0xA5

	  
	 DISP     AGU P5
	----------------
	00000000   -  A5
	00000000   -  00
	0000000a   DR 00

	  

Exceptions :

NOT YET

Example :

AGU_DR ZERO 5 0x20 
 !! Generate 64-bit address
 !! (5) add it with contents 
 !! of register 0x20 and load 
 !! it to AGU accumulator.