PROTOCOL VERIFICATION AND SIMULATION

PROTOCOL VERIFICATION AND SIMULATION

General problems:

• the protocol is capable of serving all the requirements of the information transfer;
• the protocol is properly defined;
• there is any inconsistency or redundancy in the protocol.

Problems to be solved and discovered by using LOTOS:

LOTOS - Formal Description Technique based on the Temporal Ordering Behaviour (ISO 8807)

• deadlocks;
• endless cycles on any error conditions;
• recovery from any illegal state after a given time-out period.

Problems to be solved and discovered by using VHDL:

VHDL - Hardware Description Language (IEEE-1076)

• timing problems of the DDL interface;
• overlapping transactions of the DDL protocol;
• whether the DDL protocol can be mapped to the physical medium protocol;
• how the timing of the physical medium protocol influences the DDL protocol.

The behaviour models of the FEE and the RORC will be reused in the digital system design and simulation of the interface units.

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The following main problems can be studied and solved with protocol verification and simulation, whether: ...

The LOTOS language and tools are used of the formal description and verification of the protocol. It is an international standard.

The VHDL hardware description language supports behavioural description of the digital systems. It is an IEEE standard.