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The interface units consist of two main functional parts:
In the protocol chip the 3 upper layers of the DDL protocol are implemented. The media interface realises only the lower protocol layer.
We plan to implement all the functions of the 3 upper layer in a single chip which will be a programmable logic device. It means complex logic and buffers will be implemented in this chip which is running on three different clock frequency.
The media interface interfaces the protocol chip is the physical medium. It realises only the lower protocol layer. It is able simultaneously to send and receive data with a transmission speed of 1 Gbit/s, so the signals in this sub-system can have harmonics up to 7 GHz. The PCB layout design is quite critical here, this is why we decided to build and test experimental modules before it is integrated into the interface unit.