The neurochip TOTEM: a case study in HEP

Paper: 303
Session: F (talk)
Speaker: Lazzizzera, Ignazio, INFN, Povo
Keywords: neural networks, trigger systems, parallelization

title: The neurochip TOTEM: a case study in HEP.

authors: S. Dusini, F.Ferrari, I. Lazzizzera, A. Sartori, A. Sidoti and
G. Tecchiolli

It is being proved that the neurochip TOTEM is a viable solution
for high quality and real time computational tasks in HEP, including
event classification, triggering and signal processing. The
architecture of the chip is based on a "derivative free" algorithm,
which transforms the training of a Multi-Layer-Perceptron (MLP) into a
combinatorial optimization problem, then solved by the heuristic method
called Reactive Tabu Search (RTS), highly performing even for low
precision weights. ISA, VME or PCI boards integrate the chip as a
coprocessor in a host computer.
This paper presents: 1) the state of the art and the next evolution
of the design of TOTEM; 2) its ability in the Higgs search at LHC and
the feasibility of its use as a trigger step.