OPTIONS FOR THE ATLAS LEVEL 2 TRIGGER
Paper: 466
Session: B (talk)
Speaker: Hubbard, Richard, Saclay, Gif-sur-Yvette
Keywords: ATM, large systems, switches (eg ATM, trigger algorithms, trigger systems
OPTIONS FOR THE ATLAS LEVEL 2 TRIGGER
ATLAS Level-2 Trigger Groups
R. Blair, J. Dawson, J. Schlereth
Argonne National Laboratory, USA
M. Caprini, F. Constantin
Bucharest IAP, Romania
R. Bock, A. Bogaerts, E. Denes, R.W. Dobinson,
D. Francis, S. Haas, R. Hauser, R. Heeley,
M. Liebhart, B. Martin, R. McLaren, P. Werner
CERN, Geneva, Switzerland
H. Bertelsen, M. Dam, J.R. Hansen, J.D. Hansen, B. Rensch
Niels Bohr Institute, University of Copenhagen, Denmark
Z. Hajduk, K. Korcyl
Henryk Niewodniczanski Institute of Nuclear Physics, Cracow,
Poland
I. Alexandrov, V. Kotov
Dubna JINR, Russia
O. Boyle
University of Edinburgh, U.K.
C. Hortnagl, D. Kuhn
University of Innsbruck, Austria
A. Lankford
University of California at Irvine, USA
V. Dörsing, W. Erhard, P. Kammel, A. Reinsch
Universität Jena, Germany
P. Creti, O. Palamara, S. Petrera
Universita di Lecce, Italy
P. Maley
University of Liverpool, U.K.
R. Cranfield, G. Crone, N. Woolley
University College London, U.K.
R. Hughes-Jones, S. Kolya, R. Marshall, D. Mercer
University of Manchester, U.K.
H. Högl, K. Kornmesser, A. Kugel, J. Ludvig,
R. Männer, K.-H. Noffz, S. Rühl, M. Sessler,
H. Simmler, H. Singpiel, R. Zoz
Universität Mannheim, Germany
F. Etienne, D. Laugier, Z. Qian, C. Rondot, F. Touchard
Marseille C.P.P.M, France
M. Abolins, Y. Ermoline, D. Owen, B. Pope
Michigan State University, USA
F. Rizatdinova, S. Sivoklokov
Moscow State University, Russia
R.J. Dankers, J.C. Vermeulen
NIKHEF, Amsterdam, Netherlands
P. Skubic
University of Oklahoma, USA
M. Nomachi
Osaka University, Japan
F. Harris, S. Hunt
Oxford University, U.K.
F. Hakl, M. Jirina, S. Rizek
Academy of Sciences, Prague, Czech Republic
B. Kastrup, J. Seixas, R. Weber dos Santos
Universidade Federal do Rio de Janeiro, Brazil
A. Di Mattia, S. Falciano, L. Luminari,
M. Mascagni, A. Nisati, L. Zanello
Universita di Roma "La Sapienza", Italy
A. Belias, M. Dobson, S. George,
B. Green, W. Li, N. Madsen, J. A. Strong
Royal Holloway and Bedford New College,
University of London, U.K.
J. Baines, D. Botterill, R. Middleton, F. Wickens
Rutherford Appleton Laboratory, U.K.
J. Bystricky, D. Calvet, J. Ernwein, O. Gachelin,
T. Hansl-Kozanecka, J.R. Hubbard, M. Huet, P. Le Du,
I. Mandjavidze, M. Mur, M. Smizanska, B. Thooris
DAPNIA, CEA Saclay, France
A. Ferrer, V. Gonzalez, J.M. Lopez-Amengual, E. Sanchis
Universidad de Valencia, Spain
L. Levinson
Weizmann Institute, Rehovot, Israel
D. Fasching
University of Wisconsin, USA
Contact: J.R. Hubbard, SPP/DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette,
France
Argonne National Laboratory, USA
Bucharest IAP, Romania
CERN, Geneva, Switzerland
Niels Bohr Institute, Copenhagen, Denmark
Henryk Niewodniczanski Institute of Nuclear Physics, Cracow,
Poland
Dubna JINR, Russia
University of Edinburgh, U.K.
University of Innsbruck, Austria
University of California at Irvine, USA
Universität Jena, Germany
Universita di Lecce, Italy
University of Liverpool, U.K.
University College London, U.K.
University of Manchester, U.K.
Universität Mannheim, Germany
Marseille C.P.P.M, France
Michigan State University, USA
Moscow State University, Russia
NIKHEF, Amsterdam, Netherlands
University of Oklahoma, USA
Osaka University, Japan
Oxford University, U.K.
ICS ASCR, Prague, Czech Republic
Universidade Federal do Rio de Janeiro, Brazil
Universita di Roma "La Sapienza", Italy
Royal Holloway and Bedford New College,
University of London, U.K.
Rutherford Appleton Laboratory, U.K.
DAPNIA, CEA Saclay, France
Universidad de Valencia, Spain
Weizmann Institute of Science, Rehovot, Israel
University of Wisconsin, USA
The high rate of interactions in future LHC experiments places
stringent demands on the trigger and data acquisition systems.
The first-level trigger for the ATLAS experiment is based on
special-purpose processors designed to reduce the trigger rate
from the 40 MHz beam-crossing rate to below 100 kHz.
Higher-level triggers are required to reduce the data flow
to about 100 MB/s (100 Hz with full data) for permanent storage.
Processing for the second-level trigger uses data from
regions of interest (RoIs) defined by the first-level trigger,
whereas full event data (about 1 MB per event) is used at Level-3.
The present paper presents options for the ATLAS Level-2 trigger.
Three Level-2 trigger architectures are currently under study
in a demonstrator program.
Architectures A and B are optimized for parallel processing,
with local processors extracting
features in each of the detector systems
and a global processor farm for the final Level-2 decision;
architecture A uses data-driven FPGA processors (Enable++)
for fast local feature extraction,
whereas architecture B uses general-purpose processor farms.
Architecture C is optimized for sequential processing,
with a single (global) Level-2 processor farm.
Hybrid architectures combining aspects
of architectures A, B, and C will also be tested.
The demonstrator program will include tests with
three types of switching networks: ATM, DS-link, and SCI.
In all architectures, a supervisor
receives trigger data from Level 1
and extracts the characteristics of each RoI.
It assigns processors to the events
and distributes the Level-1 trigger information
and the final Level-2 decisions.
The Level-2 architecture must satisfy
present ATLAS physics requirements,
while maintaining flexibility for unexpected future requirements.
One example of present requirements
concerns B-physics studies at low luminosity,
in which the entire tracking volume
must be scanned for low-Pt tracks.
In one of the hybrid architectures to be tested,
the initial track finding for these B-physics candidates
is performed on an Enable++ processor
under the control of the global Level-2 processor.
Investigations include optimization between Level 2 and Level 3,
since some complex algorithms,
such as the tagging of b-jets,
could be more economically performed at Level-2,
if the architecture allows direct access to data fragments.
The small-scale demonstrators
will test the critical system elements,
measure their technological limits,
and allow improved cost estimates.
Scalability will be studied on a 1024-node DS-link emulator,
on which the different architectures can be emulated.
Final system performance and scalability
will be evaluated using modelling.
Preliminary results for the various architectures studied
will be presented.