my-Enable: A FPGA-based Coprocessor proposed for Preprocessing in ATLAS
Paper: 280
Session: B (talk)
Speaker: Noffz, Klaus-Henning, Universitaet Mannheim
Keywords: algorithms, special architectures, trigger algorithms, trigger systems
A FPGA-based Coprocessor proposed for Preprocessing in ATLAS
H. Högl, A. Kugel, J. Ludvig, R. Männer, K.-H. Noffz,
S. Rühl, M. Sessler, R. Zoz
Universität Mannheim, Germany
Y. Gal, L. Levinson, M. Sidi
Weizmann Institut of Science, Rehovot, Israel
In the concept of the ATLAS LVL-2 trigger the LVL-1 event data
stream is temporarily stored during LVL-2 processing in
a huge distributed memory: the Readout Buffer (ROB) system.
In order to cope
with the enormous bandwidth of 150 GByte/s the ATLAS ROB
consists of about 1000 individual units
providing data for the LVL-2 trigger processors.
In a farm based solution for LVL-2
it is vital to limit bandwidth and computing power
requirements as much as possible. A promising possibility is
to preprocess event data at the ROB level before passing it to the
trigger processors.
Preprocessing comprises tasks to
prepare the event for the actual algorithm or to compress its
data volume to save bandwidth. Typical examples of
preprocessing algorithms are:
Coordinate transformation: Usually event data contain the
local coordinate system of the detector -- the logical numbers of
a calorimeter cell or a silicon wafer.. For effective processing
these coordinates have to be transformed into a global eta phi
coordinate system.
Partial algorithms: In some cases fractions of the actual
trigger algorithm can be executed at the preprocessing level. A good
example is the summing of cells in the calorimeter.
Most of the preprocessing tasks are not very well suited to
standard CPUs. They heavily deal with bit shuffling and
contain a strong inherent parallelism that cannot be
exploited by Von-Neumann architectures.
Dedicated hardware accelerators on the other hand would provide
an extremely effective solution. Their problem is the
missing flexibility.
FPGA processors are a new class of computers combining both
the speed of dedicated hardware solutions and the high flexibility
provided by their reconfigurability. We propose the use
of the FPGA coprocessor microEnable as a generalized preprocessing
unit for ATLAS. microEnable is a small PMC subboard currently developed
at the University of Mannheim and the Weizmann Institute.
The board can be used by its host (ROB) microprocessor as
a programmable hardware accelerator due to the high bandwidth
provided by PCI (around 100 Mbyte/s).
The board supports S-Link, the evolving ATLAS interface
standard, as an external link. It consists of a
highly complex FPGA and up to 2 Mbyte fast SRAM. It provides
interrupt and DMA capabilities.
One of the most computational intensive algorithms, the
conversion of the pixel image of the Tansition Radiation
Tracker into a coordinate list, is the first implementation
on microEnable.
Preliminary results without any optimization indicate
a processing time below 30 mus even for a worst
case occupancy of 30 %.
Assuming the mean event participation frequency of
3 kHz for a single ROB unit, microEnable is able to handle
the preprocessing for 10 ROBs.
Numbers for the full set of ATLAS preprocessing algorithms
will be provided.
The high performance of the FPGA based processing allows
the realization of microEnable as a small and inexpensive board.
Nevertheless the system is able to perform preprocessing
for a complete crate of ROBs rather than
for a single unit. It allows a very compact and cost effective
implementation of the ATLAS preprocessing system.