CALORIMETER TRIGGER ELECTRONICS FOR CMS DETECTOR AT LHC

Paper: 164
Session: B (talk)
Speaker: Dasu, Sridhara, University of Wisconsin, Madison
Keywords: data acquisition systems, trigger algorithms, trigger systems



CALORIMETER TRIGGER ELECTRONICS FOR CMS DETECTOR AT LHC

S. Dasu, M. Jaworski, J. Lackey and W. H. Smith
University of Wisconsin, Madison, WI, USA

C. Lourenco, J. Varela
CERN, Geneva, Switzerland

Ph. Busson
LPNHE, Palaiseau, France

A. Nikitenko, R. Nobrega
LIP, Lisbon, Portugal

Abstract

We present the calorimeter trigger system algorithms, electronics
design and prototype evaluation, and, simulation results for the CMS
detector at LHC. This system performs the first and only unbiased
analysis of all the CMS calorimeter data. The level-1 system uses
coarsely segmented data from calorimeter, while holding all the high
resolution data in pipeline memories in the front-end electronics, to
produce a trigger decision in 3 micro seconds. The level-1
calorimeter trigger electronics is designed to use high-speed data
paths to collect and share nearest neighbor information and perform
simple algorithms in custom integrated circuits to identify signatures
for high energy electrons, photons, neutrinos and jets. It is
implemented in 18 crates each handling 256 trigger towers. Data from
ECAL and HCAL trigger towers arrives on fiber optic cable in serial
form at 1 GBaud to one side of the 8 Receiver cards plugged into the
backside of the crate. After optical-to-electrical andserial-to-parallel conversion the data are transferred through the
card to the front side of the Receiver cards. Data in parallel form
is also shared with the neighboring crates after synchronization of
the data. The entire system operates in lock-step after this stage at
160 MHz. The energies are then summed to 4 * 4 regions using a
custom Adder ASIC. Prototypes, which sum eight 10-bit signed numbers
in 4 clock-steps at 160 MHz, have been built in GaAs technology. The
heart of the crate is a central backplane which provides data sharing
at 160 MHz. A prototype backplane has been designed and fabricated.
Data for electron isolation logic and 4 * 4 sums are
transferred to the Electron Isolation cards and Jet/Summary card
plugged into the front-side of the backplane. Electron Isolation card
implements its algorithm in another custom integrated circuit. The
candidate electrons are ranked and top candidates are passed to the
Jet/Summary card. The Jet/Summary card sorts the electron and jet
candidates in the crate to output the top four candidates of each kind
on a cable to the global trigger. It also puts out sums of E_x,
E_y and E_t in the crate using Adder ASICs. Prototype cards that
implement the data transmission and ASIC test capabilities using
boundary scan technique are being fabricated. We intend to report
results from 160 MHz inter-card data transmission on the backplane and
adder ASIC tests. A Monte Carlo program of the CMS detector,
simulating simplified geometry with parameterized detector response,
is used to study the performance of the trigger system. We also
present simulation results that indicate good efficiencies for physics
signals of interest at the LHC while limiting the background rates to
specifications of the data acquisition system.